Samsung S5PC110 Manual page 572

S5PC110_UM
1.4.1.3 Memory Chip0 Configuration Register (MemConfig0, R/W, Address=0xF000_0008, 0xF140_0008)
MEMCONFIG0
chip_base [31:24]
chip_mask [23:16]
chip_map [15:12]
chip_col [11:8]
chip_row
chip_bank
Bit
AXI Base Address
AXI base address [31:24] = chip_base
For example, if chip_base = 0x20, then AXI base address of
memory chip0 becomes 0x2000_0000.
AXI Base Address Mask
Upper address bit mask to determine AXI offset address of
memory chip0.
0 = Corresponding address bit is not to be used for comparison
1 = Corresponding address bit is to be used for comparison
For example, if chip_mask = 0xF8, then AXI offset address
becomes 0x0000_0000 ~ 0x07FF_FFFF. If AXI base address
of memory chip0 is 0x2000_0000, then memory chip0 has an
address range of 0x2000_0000 ~ 0x27FF_FFFF.
Address Mapping Method (AXI to Memory)
0x0 = Linear ({bank, row, column, width}),
0x1 = Interleaved ({row, bank, column, width}),
0x2 = Mixed1 (
if bank(MSB) = 1'b1,
{1'b1, bank(except MSB), row, column, width}
else
{1'b0, row, bank(except MSB), column, width}),
0x3 ~ 0xf = Reserved
Number of Column Address Bits
0x0 = Reserved
0x1 = 8 bits
0x2 = 9 bits
0x3 = 10 bits
0x4 = 11 bits
0x5 ~ 0xf = Reserved
[7:4] Number of Row Address Bits
0x0 = 12 bits
0x1 = 13 bits
0x2 = 14 bits
0x3 = 15 bits
0x4 ~ 0xf = Reserved
[3:0] Number of Banks
0x0 = 1 bank
0x1 = 2 banks
0x2 = 4 banks
0x3 = 8 banks
0x4 ~ 0xf = Reserved
Description
1 DRAM CONTROLLER
Initial
R/W
State
R/W DMC0:
0x20
DMC1:
0X40
R/W DMC0:
0xF0
DMC1:
0xE0
R/W 0x0
R/W 0x3
R/W 0x1
R/W 0x2
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