Adc I/O; Por - Samsung S5PC110 Manual

Risc microprocessor
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S5PC110_UM
4 POWER MANAGEMENT

4.7.6 ADC I/O

In DEEP-IDLE mode where TOP block is off, and DEEP-STOP mode where TOP block is off, the output port of
normal I/O keeps its driving value before entering DEEP-IDLE/ DEEP-STOP mode. Normal I/O has output
retention function, and it uses latch to keep its driving value. The retention control signal to input port (RTO, CPGI)
of normal I/O is generated by SYSCON when entering DEEP-IDLE/ DEEP-STOP mode. RTO is first asserted to
1'b0 to latch the output value, and then CPGI is asserted to 1'b0 to prevent leakage path from power-off block.
Finally, power-gating signal (nSCPRE, nSCALL) is asserted to 1'b0 to power off the block. RTO is 3.3V signal,
and becomes 3.3V via level-shifter.
Alive I/O also keeps its driving value from power-off region before entering DEEP-IDLE/DEEP-STOP mode.
SYSCON generates the retention control signal (CPGI).
In SLEEP mode, internal power to normal I/O is "OFF", and I/O power to normal I/O is still "ON". SYSCON
generates the retention control signal (RTO and CPGI) while entering SLEEP mode. Alive I/O changes its output
path from Normal path (power-off region) to ALIVE path (ALIVE module). RTO is asserted to 1'b0 to latch the
output value. ALIVE module drives output value of alive I/O in SLEEP mode. Read value from alive I/O goes to
ALIVE module. This read values acts as wakeup source in SLEEP mode.

4.7.7 POR

Power-On-Reset (POR) uses alive power. Thus, there is no power-down mode. The maximum current is up-to
10uA.
4-30

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