Samsung S5PC110 Manual page 453

S5PC110_UM
5.5.3.6 Minimum Limit Register (APC_MINVDD_LIMIT, R/W, Address = 0xE070_0018)
APC_MINVDD_LIMIT
Reserved
Minimum core voltage
5.5.3.7 VDD Check Register (APC_VDDCHK, R/W, Address = 0xE070_001C)
APC_VDDCHK
vddchkd[3:0]
vddchk[3:0]
5.5.3.8 VDD Delay Time Register (APC_VDDCHKD, R/W, Address = 0xE070_0020)
APC_VDDCHKD
vddchkd[11:4]
5.5.3.9 VDD Pre-delay Select Register (APC_PREDYSEL, R/W, Address = 0xE070_0024)
APC_PREDYSEL
Reserved
Pre-delay
5.5.3.10 APC Interrupt Mask Register (APC_IMASK, R/W, Address = 0xE070_0028)
APC_IMASK
Reserved
APB Write Discard
PWI Transaction Done
Error Detected in PWI
No PWI Slave Response
Output Voltage Clamped
Low VDD Timeout
Undershoot Interrupt
Bit
[7] Read undefined. Write as zero.
[6:0] Minimum SoC operating core voltage.
Bit
[7:4] The upper nibble of this register holds the four LSBs of
the 12-bit vddchkd counter.
[3:0] Evaluation time period during the integration of the slack
in the closed
Bit
[7:0] Holds the upper eight bits of the 12-bit vddchkd counter.
Bit
[7:3] Read undefined. Write as zero.
[2:0] Selects the predelay value for the HPM.
Bit
[7] Read undefined. Write as zero.
[6] The APB write is discarded.
[5] The PWI transaction is completed.
[4] Error is detected in the PWI response frame.
[3] No response frame detected on the PWI interface.
[2] The output voltage is clamped to the minimum voltage
limit or to the zero voltage.
[1] Vdd has not reached the optimum voltage in the closed-
loop mode for the voltage upward slew within the
hardware defined time period.
[0] Undershoot interrupt.
5 INTELLIGENT ENERGY MANAGEMENT
Description
Description
Description
Description
Description
Initial State
0
0x00
Initial State
0x0
0x0
Initial State
0x00
Initial State
0
0x7
Initial State
0
0
0
0
0
0
0
0
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