Samsung S5PC110 Manual page 831

S5PC110_UM
1.6.1.13 UART Interrupt Pending Register
•
UINTP0, R/W, Address = 0xE290_0030
•
UINTP1, R/W, Address = 0xE290_0430
•
UINTP2, R/W, Address = 0xE290_0830
•
UINTP3, R/W, Address = 0xE290_0C30
Interrupt pending register contains the information of the interrupts that are generated.
UINTPn
Reserved
MODEM
TXD
ERROR
RXD
If one of above 4 bits is logical high ('1'), each UART channel generates interrupt.
This register must be cleared in the interrupt service routine after clearing interrupt pending register in Interrupt
Controller (INTC). Clear specific bits of UINTP register by writing 1's to the bits that you want to clear.
1.6.1.14 UART Interrupt Source Pending Register
•
UINTSP0, R/W, Address = 0xE290_0034
•
UINTSP1, R/W, Address = 0xE290_0434
•
UINTSP2, R/W, Address = 0xE290_0834
•
UINTSP3, R/W, Address = 0xE290_0C34
Interrupt Source Pending Register contains the information of the interrupt that are generated regardless of the
value of Interrupt Mask Register
UINTSPn
Reserved
MODEM
TXD
ERROR
RXD
Bit
[31:4] Reserved
[3] Generates Modem interrupt.
[2] Generates Transmit interrupt.
[1] Generates Error interrupt.
[0] Generates Receive interrupt.
Bit
[31:4] Reserved
[3] Generates Modem interrupt.
[2] Generates Transmit interrupt.
[1] Generates Error interrupt.
[0] Generates Receive interrupt.
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Description
Description
Initial State
0
0
0
0
0
Initial State
0
0
0
0
0
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