Samsung S5PC110 Manual page 339

S5PC110_UM
3.7.5.4 Clock Gating Control Register (CLK_GATE_IP2, R/W, Address = 0xE010_0468)
CLK_GATE_IP2
CLK_TZIC3
CLK_TZIC2
CLK_TZIC1
CLK_TZIC0
CLK_VIC3
CLK_VIC2
CLK_VIC1
CLK_VIC0
Reserved
CLK_TSI
CLK_HSMMC3
CLK_HSMMC2
CLK_HSMMC1
CLK_HSMMC0
Reserved
CLK_SECJTAG
CLK_HOSTIF
CLK_MODEM
CLK_CORESIGHT
Bit Description
[31] Gating all clocks for TZIC3
(0: mask, 1: pass)
[30] Gating all clocks for TZIC2
(0: mask, 1: pass)
[29] Gating all clocks for TZIC1
(0: mask, 1: pass)
[28] Gating all clocks for TZIC0
(0: mask, 1: pass)
[27] Gating all clocks for VIC3
(0: mask, 1: pass)
[26] Gating all clocks for VIC2
(0: mask, 1: pass)
[25] Gating all clocks for VIC1
(0: mask, 1: pass)
[24] Gating all clocks for VIC0
(0: mask, 1: pass)
[23:21] Reserved
[20] Gating all clocks for TSI
(0: mask, 1: pass)
[19] Gating all clocks for HSMMC3
(0: mask, 1: pass)
[18] Gating all clocks for HSMMC2
(0: mask, 1: pass)
[17] Gating all clocks for HSMMC1
(0: mask, 1: pass)
[16] Gating all clocks for HSMMC0
(0: mask, 1: pass)
[15:12] Reserved
[11] Gating all clocks for SECJTAG
(0: mask, 1: pass)
[10] Gating all clocks for HOST I/F
(0: mask, 1: pass)
[9] Gating all clocks for MODEM
I/F
(0: mask, 1: pass)
[8] Gating all clocks for
CORESIGHT
(0: mask, 1: pass)
3 CLOCK CONTROLLER
Gated Clock Name
ACLK_TZIC3
ACLK_TZIC2
ACLK_TZIC1
ACLK_TZIC0
ACLK_VIC3
ACLK_VIC2
ACLK_VIC1
ACLK_VIC0
ACLK_TSI
ACLK_HSMMC3
SCLK_MMC3
ACLK_HSMMC2
SCLK_MMC2
ACLK_HSMMC1
SCLK_MMC1
ACLK_HSMMC0
SCLK_MMC0
PCLK_SECJTAG
ACLK_HOSTIF
ACLK_MODEM
ACLK_CSSYS
PCLK_CSSYS
Initial State
1
1
1
1
1
1
1
1
0x7
1
1
1
1
1
0xF
1
1
1
1
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