Samsung S5PC110 Manual page 334

S5PC110_UM
3.7.4.6 Clock Divider Control Register (CLK_DIV5, R/W, Address = 0xE010_0314)
CLK_DIV5
Reserved
PWM_RATIO
Reserved
SPI1_RATIO
SPI0_RATIO
3.7.4.7 Clock Divider Control Register (CLK_DIV6, R/W, Address = 0xE010_0318)
CLK_DIV6
DMC0_RATIO
PWI_RATIO
Reserved
HPM_RATIO
Reserved
COPY_RATIO
Reserved
ONENAND_RATIO
AUDIO2_RATIO
AUDIO1_RATIO
AUDIO0_RATIO
Bit
[31:12] Reserved
[15:12] DIVPWM clock divider ratio,
SCLK_PWM = MOUTPWM / (PWM_RATIO + 1)
[11:8] Reserved
[7:4] DIVSPI1 clock divider ratio,
SCLK_SPI1 = MOUTSPI1 / (SPI1_RATIO + 1)
[3:0] DIVSPI0 clock divider ratio,
SCLK_SPI0 = MOUTSPI0 / (SPI0_RATIO + 1)
Bit
[31:28] DIVDMC0 clock divider ratio,
SCLK_DMC0 = MOUTDMC0 / (DMC0_RATIO + 1)
[27:24] DIVPWI clock divider ratio,
SCLK_PWI = MOUTPWI / (PWI_RATIO + 1)
[23] Reserved
[22:20] DIVHPM clock divider ratio,
SCLK_HPM = DOUTCOPY / (IEM_RATIO + 1)
[19] Reserved
[18:16] DIVCOPY clock divider ratio,
DOUTCOPY = MOUTHPM / (COPY_RATIO + 1)
[15] Reserved
[14:12] DIVFLASH clock divider ratio,
SCLK_ONENAND = MOUTFLASH / (ONENAND_RATIO + 1)
[11:8] DIVAUDIO2 clock divider ratio,
SCLK_AUDIO2 = MOUTAUDIO2 / (AUDIO2_RATIO + 1)
[7:4] DIVAUDIO1 clock divider ratio,
SCLK_AUDIO1 = MOUTAUDIO1 / (AUDIO1_RATIO + 1)
[3:0] DIVAUDIO0 clock divider ratio,
SCLK_AUDIO0 = MOUTAUDIO0 / (AUDIO0_RATIO + 1)
Description
Description
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0x0
0x0
0x0
Initial State
0x0
0x0
0
0x0
0
0x0
0x0
0x0
0x0
0x0
0x0
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