Samsung S5PC110 Manual page 318

S5PC110_UM
3.7.2.2 PLL Control Registers (MPLL_CON, R/W, Address = 0xE010_0108)
MPLL_CON
ENABLE
Reserved
LOCKED
Reserved
VSEL
Reserved
MDIV
Reserved
PDIV
Reserved
SDIV
The reset value of APLL_CON0 and MPLL_CON generates 800 MHz and 667 MHz output clock respectively, if
the input clock frequency is 24 MHz.
Equation to calculate the output frequency:
FOUT = MDIV X FIN / (PDIV X 2
where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :
PDIV: 1 ≤ PDIV ≤ 63
MDIV: 16 ≤ MDIV ≤ 511
SDIV: 0 ≤ SDIV ≤ 5
Fref (=FIN / PDIV): 1MHz ≤ Fref ≤ 10MHz
FVCO (=MDIV X FIN / PDIV):
1000MHz ≤ FVCO ≤ 1400MHz when VSEL=LOW.
1400MHz ≤ FVCO ≤ 2000MHz when VSEL=HIGH.
FOUT: 32MHz ≤ FOUT ≤ 2000MHz
Refer to
3.3.2 Recommended PLL PMS Value for MPLL
MPLL should be turned on before entering following low-power modes. Deep idle, stop, deep stop,
Caution:
sleep mode. MPLL will be automatically turned off while entering those low-power modes.
Bit
[31] PLL enable control (0: disable, 1: enable)
[30] Reserved
[29] PLL locking indication
0 = Unlocked
1 = Locked
Read Only
[28] Reserved
[27] VCO frequency range selection
[26] Reserved
[25:16] PLL M divide value
[15:14] Reserved
[13:8] PLL P divide value
[7:3] Reserved
[2:0] PLL S divide value
SDIV
)
Description
for recommended PMS values.
3 CLOCK CONTROLLER
Initial State
0
0
0
0
0x0
0
0x14D
0
0x3
0
0x1
3-21