Samsung S5PC110 Manual page 333

S5PC110_UM
3.7.4.4 Clock Divider Control Register (CLK_DIV3, R/W, Address = 0xE010_030C)
CLK_DIV3
Reserved
FIMC_LCLK_RATIO
F1
F0
Reserved
3.7.4.5 Clock Divider Control Register (CLK_DIV4, R/W, Address = 0xE010_0310)
CLK_DIV4
UART3_RATIO
UART2_RATIO
UART1_RATIO
UART0_RATIO
MMC3_RATIO
MMC2_RATIO
MMC1_RATIO
MMC0_RATIO
Bit
[31:24] Reserved
[23:20] DIVFIMC_LCLK clock divider ratio,
SCLKFIMC_LCLK= MOUTFIMC_LCLK /
(FIMC_LCLK_RATIO + 1)
[19:16] Should have same value as FIMC_LCLK_RATIO
[15:12] Should have same value as FIMC_LCLK_RATIO
[11:0] Reserved
Bit
[31:28] DIVUART3 clock divider ratio,
SCLK_UART3 = MOUTUART3 / (UART3_RATIO + 1)
[27:24] DIVUART2 clock divider ratio,
SCLK_UART2 = MOUTUART2 / (UART2_RATIO + 1)
[23:20] DIVUART1 clock divider ratio,
SCLK_UART1 = MOUTUART1 / (UART1_RATIO + 1)
[19:16] DIVUART0 clock divider ratio,
SCLK_UART0 = MOUTUART0 / (UART0_RATIO + 1)
[15:12] DIVMMC3 clock divider ratio,
SCLK_MMC3 = MOUTMMC3 / (MMC3_RATIO + 1)
[11:8] DIVMMC2 clock divider ratio,
SCLK_MMC2 = MOUTMMC2 / (MMC2_RATIO + 1)
[7:4] DIVMMC1 clock divider ratio,
SCLK_MMC1 = MOUTMMC1 / (MMC1_RATIO + 1)
[3:0] DIVMMC0 clock divider ratio,
SCLK_MMC0 = MOUTMMC0 / (MMC0_RATIO + 1)
Description
Description
3 CLOCK CONTROLLER
Initial State
0x00
0x0
0x0
0x0
0
Initial State
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
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