Samsung S5PC110 Manual page 859

S5PC110_UM
3.4.2.3 SPI FIFO Control Register
•
MODE_CFG0, R/W, Address = 0xE130_0008
•
MODE_CFG1, R/W, Address = 0xE140_0008
MODE_CFGn
CH_WIDTH
TRAILING_CNT
BUS_WIDTH
RX_RDY_LVL
TX_RDY_LVL
Reserved
RX_DMA_SW
TX_DMA_SW
DMA_TYPE
NOTE:
1. CH_WIDTH is shift-register width.
2. BUS_WIDTH is SPI FIFO width, transfer data size should be aligned at BUS_WIDTH.
3. CH_WIDTH must be smaller than BUS_WIDTH or same.
Bit
[30:29] 00 = Byte
01 = Halfword
10 = Word
11 = Reserved
[28:19] Count value from writing the last data in RX FIFO to flush
trailing bytes in FIFO
00 = Byte
01 = Halfword
[18:17]
10 = Word
11 = Reserved
[16:11] Rx FIFO trigger level in INT mode.
Port 0: trigger level (bytes) = 4 x N
Port 1: trigger level (bytes) = N
(N = value of RX_RDY_LVL field)
[10:5] Tx FIFO trigger level in INT mode.
Port 0: trigger level (bytes) = 4 x N
Port 1: trigger level (bytes) = N
(N = value of TX_RDY_LVL field)
[4:3] Reserved
[2] Rx DMA mode enable/disable
0 = Disables DMA Mode
1 = Enables DMA Mode
[1] Tx DMA mode on/off
0 = Disables DMA Mode
1 = Enables DMA Mode
[0] DMA transfer type, single or 4 busts.
0 = Single
1 = 4 burst
DMA transfer size must be set as the same size in SPI DMA.
3 SERIAL PERIPHERAL INTERFACE
Description Initial State
0
0
0
0
0
-
0
0
0
3-11