S5PC110_UM
5.8.3.10 Device Mode Receive Status Debug Read/Status Read and Pop Registers (GRXSTSR/GRXSTSP,
R, Address = 0xEC00_001C, 0xEC00_0020)
GRXSTSR/
Bit
GRXSTSP
Reserved
[31:25]
FN
[24:21]
PktSts
[20:17]
DPID
[16:15]
BCnt
[14:4]
EPNum
[3:0]
5.8.3.11 Receive FIFO Size Register (GRXFSIZ, R/W, Address = 0xEC00_0024)
The application programs the RAM size that must be allocated to the RxFIFO.
GRXFSIZ
Bit
Reserved
[31:16]
RxFDep
[15:0]
-
Frame Number
This is the least significant 4 bits of the (micro) frame number in
which the packet is received on the USB. This field is
supported if isochronous OUT endpoints are supported.
Packet Status
Indicates the status of the received packet.
4'b0001: Global OUT NAK (triggers an interrupt)
•
4'b0010: OUT data packet received
•
4'b0011: OUT transfer completed (triggers an interrupt)
•
4'b0100: SETUP transaction completed (triggers an interrupt)
•
4'b0110: SETUP data packet received
•
others: Reserved
•
Data PID
Indicates the Data PID of the received OUT data packet.
2'b00: DATA0
•
2'b10: DATA1
•
2'b01: DATA2
•
2'b11: MDATA
•
Byte Count
Indicates the byte count of the received data packet.
Endpoint number
Indicates the endpoint number to which the current received
packet belongs.
-
RxFIFO Depth
This value is in terms of 32-bit words.
Minimum value is 16
•
Maximum value is 7936
•
The power-on reset value of this register is specified as the
Largest Rx Data FIFO Depth.
A new value must be written to this field. Programmed values
must not exceed the power-on value set.
Description
Description
5 USB2.0 HS OTG
R/W
Initial State
-
7'h3F
R
4'hF
R
4'b1111
R
2'b11
R
11'h3FF
R
4'hF
R/W
Initial State
-
16'h0
R/W
16'h1F00
5-46