Samsung S5PC110 Manual page 881

S5PC110_UM
5.6 REGISTER MAP
5.6.1 OVERVIEW OF REGISTER MAP
To control and observe the OTG PHY, access the USB PHY control registers based on the address EC10_0000h.
The OTG Link Core registers is based on the address EC00_0000h, which is classified as follows:
•
Core Global Registers
•
Host Mode Registers
−
Host Global Registers
−
Host Port CSRs
−
Host Channel-Specific Registers
•
Device Mode Registers
−
Device Global Registers
−
Device Endpoint-Specific Registers
The Core Global and Host Port control and status registers are accessed in both Host and Device modes. If the
OTG Link operates in either Device or Host mode, the application must not access registers from other modes. If
an unauthorized access occurs, a Mode Mismatch interrupt is generated and value is reflected in the Core
Interrupt register. If the core switches from one mode to another, reprogram the registers in the new mode of
operation to match state after a power-on reset.
5 USB2.0 HS OTG
5-5