S5PC110_UM
1.2.1.2 Channel Control Register for DMA_PERI(0,1) (CC, R)
•
CC_0, R, Address = 0xE090_0408, 0xE0A0_0408
•
CC_1, R, Address = 0xE090_0428, 0xE0A0_0428
•
CC_2, R, Address = 0xE090_0448, 0xE0A0_0448
•
CC_3, R, Address = 0xE090_0468, 0xE0A0_0468
•
CC_4, R, Address = 0xE090_0488, 0xE0A0_0488
•
CC_5, R, Address = 0xE090_04A8, 0xE0A0_04A8
•
CC_6, R, Address = 0xE090_04C8, 0xE0A0_04C8
•
CC_7, R, Address = 0xE090_04E8, 0xE0A0_04E8
CCn
D
st_burst_size
src_burst_size
Bit
[17:15] Programs the burst size that DMAC uses when it writes the
destination data.
b000 = 1 byte
b001 = 2 bytes
b010 = 4 bytes
Other = Reserved
[3:1]
Programs the burst size that DMAC uses when it reads the
source data.
b000 = 1 byte
b001 = 2 bytes
b010 = 4 bytes
Other = Reserved
Description
1 DMA CONTROLLER
Initial State
0
0
1-18