I/O Interface - Samsung S5PC110 Manual

S5PC110_UM

3.7 I/O INTERFACE

Signal
ADDR[15:0]
DQ[15:0]
nCE[1:0]
nWE
nOE
INT[1:0]
nAVD
nRP
CLK
NOTE: The INT pin of each OneNAND Device must be pulled up by a 4.7K-ohm external pull-up resistor.
I/O
Address Bus outputs, during memory read/ write
I/O
address phase
Data Bus outputs address during memory read/ write
address phase, inputs data during memory read data
I/O
phase and outputs data during memory write data
phase.
Chip Selects are activated when the address of a
memory is within the address region of each bank.
Xm0CSn[3:2] can be assigned to either SROMC or
O
OneNAND controller by System Controller SFR setting.
Active LOW.
Write Enable indicates that the current bus cycle is a
O
write cycle. Active LOW.
Output Enable indicates that the current bus cycle is a
O
read cycle. Active LOW.
Interrupt inputs from OneNAND memory Bank 0, 1.
I
If OneNAND memory is not used, these signals should
be tied to zero.
Address valid output. In the POP products, address and
O data are multiplexed. Xm0ADDRVALID indicate when
the bus is used for address. Active LOW.
System reset output for OneNAND memory.
O
Active LOW.
Static memory clock for synchronous static memory
O
devices.
Description
3 ONENAND CONTROLLER
PAD Type
Xm0ADDR
muxed
[15:0]
Xm0DATA
muxed
[15:0]
Xm0CSn
muxed
[5:4]
Xm0WEn muxed
Xm0OEn muxed
Xm0FRnB
muxed
[5:4]
Xm0FCLE muxed
Xm0FWEn muxed
Xm0FALE muxed
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