Samsung S5PC110 Manual page 417

S5PC110_UM
4.10.5.7 MISC Register (ADC_CONTROL, R/W, Address = 0xE010_E818)
ADC_CONTROL
Reserved
DISABLE
4.10.5.8 MISC Register (PS_HOLD_CONTROL, R/W, Address = 0xE010_E81C)
PS_HOLD_CONTROL
Reserved
Reserved
DIR
DATA
Reserved
PS_HOLD_OUT_EN
PS_HOLD (muxed with XEINT[0]) pin value is kept up in any power mode. This register is in alive region and reset
by XnRESET or power off only.
4.10.5.9 MISC Register
•
INFORM0, R/W, 0xE010_F000
•
INFORM1, R/W, 0xE010_F004
•
INFORM2, R/W, 0xE010_F008
•
INFORM3, R/W, 0xE010_F00C
•
INFORM4, R/W, 0xE010_F010
•
INFORM5, R/W, 0xE010_F014
•
INFORM6, R/W, 0xE010_F018
INFORMn
INFORM
Bit
[31:1] Reserved
[0] TS-ADC enable control
(0: disable, 1: enable)
Bit
[31:12] Reserved
[11:10] Reserved
[9] Direction (0: input, 1: output)
[8] Driving value (0:low, 1:high)
[7:1] Reserved
[0] XEINT[0] pad is controlled by this register values and
values of control registers for XEINT[0] of GPIO
chapter is ignored when this field is '1'.
(0: disable, 1: enable)
Bit
[31:0] User defined information register. INFORM0~3
registers are cleared by asserting XnRESET pin.
INFORM4~6 registers are cleared by power off only.
Description
Description
Description
4 POWER MANAGEMENT
Initial State
0x0000_0000
1
Initial State
0x00005
0
1
0
0x00
0
Initial State
0x0000_0000
4-57