Samsung S5PC110 Manual page 452

S5PC110_UM
5.5.3.4 APC Control Register (APC_CONTROL, R/W, Address = 0xE070_0010)
APC_CONTROL
APC_HPM_AUTH_SET
APC_PWRSV_EN
APC_MULTICAL_EN
APC_HPM_EN
APC_PWRDN_EN
APC_PLL_STATE_DETECT
APC_LOOP_MODE
APC_VDD_UD
5.5.3.5 APC Status Register (APC_STATUS, R, Address = 0xE070_0014)
APC_STATUS
Reserved
AUTH_DONE
PWI_BUSY
POWERWISE
_VERIFIED
VDDOK
Bit
[7] HPM is set to the ring oscillator mode for a random PC
used in the authentication sequence.
[6] Enables the power save mode. On setting this bit:
* the apc_refclk_req signal is deasserted when the
apc_refclk_c clock signal is not required
* the CMU can gate off the clock signal to save the
power when the apc_refclk_req signal is deasserted.
[5] Enables the multiple RCC mode. Default, the APC1 is in
the single RCC mode.
[4] Enables the HPM. Default, the HPM is disabled and the
PC is zero.
[3] Enables the PWI sleep and wakeup command
functions. Default, this feature is disabled.
[2] Enable bit for disabling closed loop mode when pll is
unstable.
[1] Enable bit for the closed-loop or the open-loop mode:
* defaults to the open-loop mode
* setting this bit enables the closed-loop mode.
The voltage scaling in the open-loop or the closed-loop
mode is enabled only after setting the APC_VDD_UD bit
of the APC_CONTROL Register.
[0] Enables voltage scaling feature in the APC1:
* defaults to the fixed voltage mode and the core voltage
is set to the maximum value
* for the closed-loop and the open-loop modes this bit
must be enabled.
Bit
[7:4] Read undefined.
[3] Authentication procedure is completed.
[2] Bit is set on initiating a PWI command and is cleared
when the command sequence is completed.
[1] Bit is set on a successful PowerWise capable power
supply authentication.
[0] Vdd level is suitable for the current target frequency.
This bit is set in the closed-loop mode.
5 INTELLIGENT ENERGY MANAGEMENT
Description
Description
Initial State
0
0
0
0
0
0
0
0
Initial State
0
0
0
0
0
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