Samsung S5PC110 Manual page 933

S5PC110_UM
5.8.5 HOST MODE REGISTERS ( HOST PORT CONTROL AND STATUS REGISTERS)
5.8.5.1 Host Port Control and Status Register (HPRT, R/W, Address = 0xEC00_0440)
This register is available only in Host mode. Currently, the OTG Host supports only one port. A single register
holds USB port-related information such as USB reset, enable, suspend, resume, connect status, and test mode
for each port. On a Port Interrupt, the application must read this register and clear the bit that caused the interrupt.
For the R_SS_WC bits, the application must write a 1 to the bit to clear the interrupt
HPRT Bit
Reserved [31:19] -
PrtSpd [18:17] Port Speed
PrtTstCtl [16:13] Port Test Control
PrtPwr [12]
PrtLnSts [11:10] Port Line Status
Reserved [9]
Indicates the speed of the device attached to this port.
2'b00: High speed
•
2'b01: Full speed
•
2'b10: Low speed
•
2'b11: Reserved
•
The application writes a nonzero value to this field to put the
port into a Test mode, and the corresponding pattern is signaled
on the port.
4'b0000: Test mode disabled
•
4'b0001: Test_J mode
•
4'b0010: Test_K mode
•
4'b0011: Test_SE0_NAK mode
•
4'b0100: Test_Packet mode
•
4'b0101: Test_Force_Enable
•
Others: Reserved
•
Port Power
The application uses this field to control power to this port, and
the core clears this bit on an overcurrent condition.
1'b0: Power off
•
1'b1: Power on
•
Indicates the current logic level USB data lines
Bit [10]: Logic level of D −
•
Bit [11]: Logic level of D+
•
-
Description
5 USB2.0 HS OTG
R/W Initial State
- 13'h0
R 2'b0
R/W 4'h0
R_W_ 1'b0
SC
R 2'b0
- 1'b0
5-57