Clock Mux Status Sfrs - Samsung S5PC110 Manual

S5PC110_UM

3.7.8 CLOCK MUX STATUS SFRS

3.7.8.1 Clock MUX Status SFRs (CLK_MUX_STAT0, R, Address = 0xE010_1100)
Clock MUX status registers show the status of glitch-free MUX logic. When CLK_SRCx SFR has been changed, it
takes several clock cycles. Therefore, S/W should check the status of glitch-free MUX if the SFR values are
applied.
CLK_MUX_STAT0
Reserved
ONENAND_SEL
Reserved
MUX_PSYS_SEL
Reserved
MUX_DSYS_SEL
Reserved
MUX_MSYS_SEL
Reserved
VPLL_SEL
Reserved
EPLL_SEL
Reserved
MPLL_SEL
Reserved
APLL_SEL
Bit
[31] Reserved
[30:28] Selection signal status of MUXFLASH
(001:HCLK_PSYS, 010:HCLK_DSYS, 1xx: On changing)
[27] Reserved
[26:24] Selection signal status of MUX_PSYS
(001:SCLKMPLL, 010:SCLKA2M, 1xx: On changing)
[23] Reserved
[22:20] Selection signal status of MUX_DSYS
(001:SCLKMPLL, 010:SCLKA2M, 1xx: On changing)
[19] Reserved
[18:16] Selection signal status of MUX_MSYS
(001:SCLKAPLL, 010:SCLKMPLL, 1xx: On changing)
[15] Reserved
[14:12] Selection signal status of MUXVPLL
(001: FINVPLL, 010: FOUTVPLL, 1xx: On changing)
[11] Reserved
[10:8] Selection signal status of MUXEPLL
(001:FINPLL, 010:FOUTEPLL, 1xx: On changing)
[7] Reserved
[6:4] Selection signal status of MUXMPLL
(001:FINPLL, 010:FOUTMPLL, 1xx: On changing)
[3] Reserved
[2:0] Selection signal status of MUXAPLL
(001:FINPLL, 010:FOUTAPLL, 1xx: On changing)
Description
3 CLOCK CONTROLLER
Initial State
0
0x1
0
0x1
0
0x1
0
0x1
0
0x1
0
0x1
0
0x1
0
0x1
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