Samsung S5PC110 Manual page 829

S5PC110_UM
1.6.1.12 UART Channel Dividing Slot Register
•
UDIVSLOT0, R/W, Address = 0xE290_002C
•
UDIVSLOT1, R/W, Address = 0xE290_042C
•
UDIVSLOT2, R/W, Address = 0xE290_082C
•
UDIVSLOT3, R/W, Address = 0xE290_0C2C
UDIVSLOT n
Reserved [31:16]
UDIVSLOTn [15:0]
1. UART Baud Rate Configuration
There are four UART baud rate divisor registers in the UART block, namely, UBRDIV0, UBRDIV1, UBRDIV2
and UBRDIV3.
The value stored in the baud rate divisor register (UBRDIVn) and dividing slot register(UDIVSLOTn) is used to
determine the serial Tx/Rx clock rate (baud rate) as follows:
DIV_VAL = UBRDIVn + (num of 1's in UDIVSLOTn)/16
DIV_VAL = (PCLK / (bps x 16)) −1
or
DIV_VAL = (SCLK_UART / (bps x 16)) −1
Where, the divisor should be from 1 to (216-1).
Using UDIVSLOT, you can generate the baud rate more accurately.
For example, if the baud-rate is 115200 bps and SCLK_UART is 40 MHz, UBRDIVn and UDIVSLOTn are:
DIV_VAL = (40000000 / (115200 x 16)) -1
= 21.7 -1
= 20.7
UBRDIVn = 20 ( integer part of DIV_VAL )
(num of 1's in UDIVSLOTn)/16 = 0.7
then, (num of 1's in UDIVSLOTn) = 11
so, UDIVSLOTn can be 16'b1110_1110_1110_1010 or 16'b0111_0111_0111_0101, etc.
Bit
Reserved
Select the slot where clock generator divide clock source
1 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER
Description Initial State
0
0x0000
1-27