Onenand Interface Register - Samsung S5PC110 Manual

S5PC110_UM

3.8.2 ONENAND INTERFACE REGISTER

3.8.2.1 OneNAND Interface Control Register (ONENAND_IF_CTRL, R/W, Address = 0xB060_0100)
ONENAND_
Bit
IF_CTRL
MUX [31]
- [30:27]
GCE [26]
- [25:18]
RPE [17]
- [16]
RM [15]
BRWL [14:12]
Mux or Demux OneNAND Type Select
OneNAND interface supports both Demux and Mux type OneNAND
devices. This bit is used to specify whether OneNAND is Demux or
Mux type. The value of OM pins determines the reset value of this bit
If the OM pins are of Demuxed type OneNAND boot, the reset value
of this bit is 1. Otherwise, the reset value is 0. (For more information,
refer to Chapter 2.6. Booting Sequence)
0b = Mux type
1b = Demux type
Reserved
Gated Clock Enable
To reduce power consumption, OneNAND interface supports gated
clock method. If this bit is set, the OneNAND clock toggles only
during OneNAND read/ write execution time.
0b = Disable
1b = Enable
Reserved
Enables Read Prefetch.
This bit is used to enable or disable the read prefetch operation of
the OneNAND interface.
0b = Read Prefetch Disable
1b = Read Prefetch Enable
OneNAND Interface has its own read prefetch FIFO. This FIFO is
implemented as an asynchronous FIFO of 32-bit x 32-depth between
AHB and OneNAND clock domains. If the sequential read access is
dominant, prefetch next read data in advance to increase the
OneNAND read bandwidth.
If Read Prefetch Enable (RPE) bit is set to 1 OneNAND interface will
start to prefetch read data when it receives AHB read request. If the
read prefetch FIFO becomes full during the prefetch operation, the
prefetch operation will be stopped immediately. As soon as the read
prefetch FIFO is ready to accept the next read data by successive
AHB read operation, the prefetch operation will be resumed. If the
read prefetch address reaches 1-KByte aligned address during the
prefetch operation, the prefetch operation will be stopped.
Reserved
Read Mode
This bit is used to select the OneNAND read mode between
synchronous and asynchronous modes.
0b = Asynchronous Read
1b = Synchronous Read
Burst Read Write Latency
Description
3 ONENAND CONTROLLER
Initial State
1b or 0b
-
0b
-
0b
-
0b
100b
3-23