Samsung S5PC110 Manual page 909

S5PC110_UM
5.8.3.3 OTG AHB Configuration Register (GAHBCFG, R/W, Address = 0xEC00_0008)
This register configures the core after power-on or a change in mode of operation. This register mainly contains
AHB system-related configuration parameters. Do not change this register after the initial programming. The
application must program this register before starting any transactions on either the AHB or the USB.
GAHBCFG Bit
Reserved [31:9]
PTxFEmpLvl [8]
NPTxFEmp [7]
Lvl
Reserved [6]
DMAEn [5]
HBstLen [4:1]
GlblIntrMsk [0]
-
Periodic TxFIFO Empty Level
Indicates if the Periodic TxFIFO Empty Interrupt bit in the Core
Interrupt registers (GINTSTS.PTxFEmp) is triggered. This bit is
used only in Slave mode.
1'b0: GINTSTS.PTxFEmp interrupt indicates that the Periodic
•
TxFIFO is half empty
1'b1: GINTSTS.PTxFEmp interrupt indicates that the Periodic
•
TxFIFO is completely empty
Non-Periodic TxFIFO Empty Level
This bit is used only in Slave mode. This bit indicates when IN
endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp)is
triggered.
1'b0: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint
•
TxFIFO is half empty
1'b1: DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint
•
TxFIFO is completely empty
-
DMA Enable
1'b0: Core operates in Slave mode
•
1'b1: Core operates in a DMA mode
•
Burst Length/vType
Internal DMA Mode − AHB Master burst type:
4'b0000: Single
•
4'b0001: INCR
•
4'b0011: INCR4
•
4'b0101: INCR8
•
4'b0111: INCR16
•
Others: Reserved
•
Global Interrupt Mask
The application uses this bit to mask or unmask the interrupt line
assertion. Irrespective of this bit's setting, the interrupt status
registers are updated by the core
1'b0: Mask the interrupt assertion to the application
•
1'b1: Unmask the interrupt assertion to the application
•
Description
5 USB2.0 HS OTG
R/W Initial State
- 23'h0
R/W 1'b0
R/W 1'b0
- 1'b0
R/W 1'b0
R/W 4'b0
R/W 1'b0
5-33