Samsung S5PC110 Manual page 918

S5PC110_UM
GINTSTS Bit
OTGInt [2]
ModeMis [1]
CurMod [0]
OTG Interrupt
The core sets this bit to indicate an OTG protocol event. The
application must read the OTG Interrupt Status (GOTGINT)
register to determine the exact event that caused this interrupt.
The application must clear the appropriate status bit in the
GOTGINT register to clear this bit.
Mode Mismatch Interrupt
The core sets this bit if the application is trying to access:
A Host mode register, if the core is operating in Device mode
•
A Device mode register, if the core is operating in Host mode
•
Current Mode Of Operation
Indicates the current mode of operation.
1'b0: Device mode
•
1'b1: Host mode
•
Description
5 USB2.0 HS OTG
R/W Initial State
R 1'b0
R_SS 1'b0
_WC
R 1'b0
5-42