Samsung S5PC110 Manual page 862

S5PC110_UM
3.4.2.6 SPI Status Register
•
SPI_STATUS0, R, Address = 0xE130_0014
•
SPI_STATUS1, R, Address = 0xE140_0014
SPI_STATUSn
TX_DONE
TRAILING_BYTE
RX_FIFO_LVL
TX_FIFO_LVL
RX_OVERRUN
RX_UNDERRUN
TX_OVERRUN
TX_UNDERRUN
RX_FIFO_RDY
TX_FIFO_RDY
Bit
[25] Indication of transfer done in Shift register(master mode only)
0 = All case except blow case
1 = If Tx FIFO and shift register are empty
[24] Indication that trailing count is 0
[23:15] Data level in Rx FIFO
0 ~ 256 bytes in port 0
0 ~ 64 bytes in port
[14:6] Data level in Tx FIFO
0 ~ 256 bytes in port 0
0 ~ 64 bytes in port
[5] Rx FIFO overrun error
0 = No Error
1 = Overrun Error
[4] Rx FIFO underrun error
0 = No Error,
1 = Underrun Error
[3] Tx FIFO overrun error
0 = No Error
1 = Overrun Error
[2] Tx FIFO underrun error
Tx FIFO underrun error is occurred if TX FIFO is empty in slave
mode.(no empty state in slave Tx mode)
0 = No Error
1 = Underrun Error
[1] 0 = Data in FIFO less than trigger level
1 = Data in FIFO more than trigger level
[0] 0 = Data in FIFO more than trigger level
1 = Data in FIFO less than trigger level
3 SERIAL PERIPHERAL INTERFACE
Description Initial State
0
0
0
0
0
0
0
0
0
0
3-14