S5PC110_UM
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24-channel DMA controller (8 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA)
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Supports 14x8 key matrix
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10-channel 12-bit multiplexed ADC
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Configurable GPIOs
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Real time clock, PLL, timer with PWM and watch dog timer
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System timer support for accurate tick time in power down mode (except sleep mode)
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Memory Subsystem
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Asynchronous SRAM/ ROM/ NOR Interface with x8 or x16 data bus
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NAND Interface with x8 data bus
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Muxed/ Demuxed OneNAND Interface with x16 data bus
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LPDDR1 Interface with x16 or x32 data bus (266~400 Mbps/ pin DDR)
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DDR2 interface with x16 or x32 data bus (400 Mbps/ pin DDR)
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LPDDR2 interface (400 Mbps/ pin DDR)
1.3.1 MICROPROCESSOR
The key features of this microprocessor include:
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The ARM CortexTM-A8 processor is the first application processor based on ARMv7 architecture.
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With the ability to scale in speed from 600 MHz to 1 GHz (or more), the ARM CortexTM-A8 processor meets
the requirements of power-optimized mobile devices, which require operation in less than 300mW; and
performance-optimized consumer applications require 2000 Dhrystone MIPS.
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Supports first superscalar processor featuring technology from ARM for enhanced code density and
performance, NEONTM technology for multimedia and signal processing, and Jazelle® RCT technology for
ahead-of-time and just-in-time compilation of Java and other byte code languages.
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Other features of ARM CortexTM-A8 include:
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Thumb-2 technology for greater performance, energy efficiency, and code density
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NEONTM signal processing extensions
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Jazelle RCT Java-acceleration technology
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TrustZone technology for secure transactions and DRM
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13-stage main integer pipeline
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10-stage NEONTM media pipeline
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Integrated L2 Cache using standard compiled RAMs
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Optimized L1 caches for performance and power
1 OVERVIEW OF S5PC110
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