Samsung S5PC110 Manual page 608

S5PC110_UM
The corresponding commands must be issued to the device command register (Command register (device
address offset: 0x1E440)). For more information about the OneNAND device memory map, refer to
shows the data path when the external AHB master accesses control registers.
OneNAND Controller
OneNAND
Interface
Reserved
Reserved
Control
Registers
Reserved
Table 3-1 OneNAND Controller Memory Map
Address (Start)
0xB0000000
0xB0020000
0xB0040000
0xB0060000
0xB0080000
0xB00A0000
0xB00C0000
0xB00E0000
0xB0100000
0xB0120000
0xB0140000
0xB0160000
0xB0180000
0xB01A0000
0xB01C0000
0xB01E0000
0xB0200000
0xB0400000
0xB0600000
0xB0800000
OneNAND Controller
Address (End)
0xB001FFFF
0xB003FFFF
0xB005FFFF
0xB007FFFF
0xB009FFFF
0xB00BFFFF
0xB00DFFFF
0xB00FFFFF
0xB011FFFF
0xB013FFFF
0xB015FFFF
0xB017FFFF
0xB019FFFF
0xB01BFFFF
0xB01DFFFF
0xB01FFFFF
0xB03FFFFF
0xB05FFFFF
0xB07FFFFF
0xB0FFFFFF
3 ONENAND CONTROLLER
Window
Size
OneNAND nCE[0]
(For more information about
128KB
OneNAND Chip #0 address
map, refer to
128KB Reserved for future use
128KB OneNAND nCE[1]
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
128KB Reserved for future use
2MB Reserved for future use
2MB Reserved for future use
2MB 32-bit Registers
8MB Reserved for future use
that
Figure 3-3
Note
Table 3-3.
3-6