Samsung S5PC110 Manual page 502

Risc microprocessor
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S5PC110_UM
3.4.1.1 Secure RAM Region Size Register (TZPCR0SIZE(TZPC0), RW, Address = 0xF150_0000)
TZPCR0SIZE
Reserved
R0Size
3.4.1.2 Decode Protection 0-3 Status Registers
TZPCDECPROTxSTAT(TZPC0), R, Address = 0xF150_0800, 0xF150_080C, 0xF150_0818
TZPCDECPROTxSTAT(TZPC1), R, Address = 0xFAD0_0800, 0xFAD0_080C, 0xFAD0_0818
TZPCDECPROTxSTAT(TZPC2), R, Address = 0xE060_0800, 0xE060_080C, 0xE060_0818
TZPCDECPROTxSTAT(TZPC3), R, Address = 0xE1C0_0800, 0xE1C0_080C, 0xE1C0_0818
TXPCDECPROTxStat
Reserved
DECPROTxStat
Bit
[31:6]
Read undefined. Write as zero.
[5:0]
Secure RAM region size in 4KB steps.
0x00000000 = no secure region
0x00000001 = 4KB secure region
0x00000002 = 8KB secure region
...
0x0000001F = 128KB secure region
0x00000020 or above sets the entire RAM to secure
regardless of size
Bit
[31:8]
Read undefined.
[7:0]
Show the status of the decode protection output:
0 = Decode region corresponding to the bit is secure
1 = Decode region corresponding to the bit is non-secure
There is one bit of the register for each protection output,
eight outputs are implemented as standard.
3 ACCESS CONTROLLER (TZPC)
Description
Description
Initial State
0
0x0
Initial State
0
0x000
3-9

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