Samsung S5PC110 Manual page 948

S5PC110_UM
5.8.7.5 Device OUT Endpoint Common Interrupt Mask Register (DOEPMSK, R/W, Address = 0xEC00_0814)
This register works with each of the Device OUT Endpoint Interrupt registers for all endpoints to generate an
interrupt per OUT endpoint. The OUT endpoint interrupts for a specific status in the DOEPINTn register is masked
by writing to the corresponding bit in this register. Status bits are masked by default.
•
Mask interrupt: 1'b0
•
Unmask interrupt: 1'b1
DOEPMSK
Reserved
BnaOutIntrMsk
OutPktErrMsk
Reserved
Back2BackSETup
Reserved
OUTTknEPdisMsk
SetUPMsk
AHBErrMsk
EPDisbldMsk
XferComplMsk
5.8.7.6 Device ALL Endpoints Interrupt Register (DAINT, R, Address = 0xEC00_0818)
If a significant event occurs on an endpoint, a Device All Endpoints Interrupt register interrupts the application
using the Device OUT Endpoints Interrupt bit or Device IN Endpoints Interrupt bit of the Core Interrupt register.
There is one interrupt bit per endpoint, up to a maximum of 16 bits for OUT endpoints and 16 bits for IN endpoints.
For a bidirectional endpoint, the corresponding IN and OUT interrupt bits are used. Bits in this register are set and
cleared if the application sets and clears bits in the corresponding Device Endpoint − n Interrupt register.
DAINT
OutEPInt
InEpInt
Bit
[31:10] -
[9] BNA interrupt Mask
[8] OUT Packet Error Mask
[7] -
[6] Back-to-Back SETUP Packets Received Mask
Applies to control OUT endpoints only.
[5] -
[4] OUT Token Received When Endpoint Disabled
Applies to control OUT endpoints only.
[3] SETUP Phase Done Mask
Applies to control endpoints only.
[2] AHB Error
[1] Endpoint Disabled Interrupt Mask
[0] Transfer Completed Interrupt Mask
Bit
[31:16] OUT Endpoint Interrupt Bits
One bit per OUT endpoint :
Bit 16 for OUT endpoint 0, bit 31 for OUT endpoint 15
[15:0] IN Endpoint Interrupt Bits
One bit per IN endpoint :
Bit 0 for IN endpoint 0, bit 15 for endpoint 15
Description
Description
5 USB2.0 HS OTG
R/W Initial State
- 22'h0
R/W 1'b0
R/W 1'b0
- -
R/W 1'b0
- 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W 1'b0
R/W Initial State
R 16'h0
R 16'h0
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