Clock Source Control Registers - Samsung S5PC110 Manual

S5PC110_UM

3.7.3 CLOCK SOURCE CONTROL REGISTERS

S5PC110 has many clock sources, which include four PLL outputs, the external oscillator, the external clock, and
other clock sources from GPIO. CLK_SRCn registers control the source clock of each clock divider.
3.7.3.1 Clock Source Control Registers (CLK_SRC0, R/W, Address = 0xE010_0200)
CLK_SRC0
Reserved
ONENAND_SEL
Reserved
MUX_PSYS_SEL
Reserved
MUX_DSYS_SEL
Reserved
MUX_MSYS_SEL
Reserved
VPLL_SEL
Reserved
EPLL_SEL
Reserved
MPLL_SEL
Reserved
APLL_SEL
Bit
[31:29] Reserved
[28] Control MUXFLASH (0:HCLK_PSYS, 1:HCLK_DSYS)
[27:25] Reserved
[24] Control MUX_PSYS (0:SCLKMPLL, 1:SCLKA2M)
[23:21] Reserved
[20] Control MUX_DSYS (0:SCLKMPLL, 1:SCLKA2M)
[19:17] Reserved
[16] Control MUX_MSYS (0:SCLKAPLL, 1:SCLKMPLL)
[15:13] Reserved
[12] Control MUXVPLL (0: FINVPLL, 1: FOUTVPLL)
[11:9] Reserved
[8] Control MUXEPLL (0:FINPLL, 1:FOUTEPLL)
[7:5] Reserved
[4] Control MUXMPLL (0:FINPLL, 1:FOUTMPLL)
[3:1] Reserved
[0] Control MUXAPLL (0:FINPLL, 1:FOUTAPLL)
Description
3 CLOCK CONTROLLER
Initial State
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0
0x0
0
3-25