Samsung S5PC110 Manual page 454

S5PC110_UM
5.5.3.11 APC Interrupt Status Register (APC_ISTATUS, R, Address = 0xE070_002C)
APC_ISTATUS
Reserved
APB Write Discard
PWI Transaction Done
Error Detected in PWI
No PWI Slave Response
Output Voltage Clamped
Low VDD Timeout
Undershoot Interrupt
5.5.3.12 APC Interrupt Clear Register (APC_ICLEAR, W, Address = 0xE070_0030)
APC_ICLEAR
Reserved
APB Write Discard
PWI Transaction Done
Error Detected in PWI
No PWI Slave Response
Output Voltage Clamped
Low VDD Timeout
Undershoot Interrupt
Bit
[7] Read undefined.
[6] When the PWI command is active in the APC1, the new
PWI commands issued by the host are discarded. This
discarded status is reflected in this bit.
[5] Bit is set when the APC1 completes the host issued PWI
command. Software has to check this bit as well as the
APC_STATUS.PWI_BUSY bit to confirm the completion
of the command.
[4] Bit is set on an error response from the PWI slave for the
host issued as well as the APC1 issued PWI commands.
[3] Bit is set for no response from the PWI slave for the host
issued as well as the APC1 issued commands.
[2] This bit is set when the output voltage is clamped to the
minimum limit or to the zero voltage.
[1] During upward voltage slew, this bit is set in the closed-
loop mode indicating that the dynamic compensator is
not able to increase the voltage to the required level for
the new higher performance level within the maximum
time period set by the hardware.
[0] In the closed-loop AVS operation for a performance
level change after reaching the optimum voltage the
APC1 asserts an interrupt if the voltage correction
continues and results in a slack error (+ve) which is more
than the undershoot_limit value programmed in the
APC_UNSHT_NOISE Register for nine consecutive
samples.
Bit
[7] Undefined. Write as zero.
[6] The APB write is discarded.
[5] The PWI transaction is completed.
[4] Error is detected in PWI response frame.
[3] No response frame is detected on PWI interface.
[2] The output voltage is clamped to minimum limit or zero
voltage.
[1] In the closed-loop mode, Vdd has not reached the target
voltage in the programmed time period for the upward
voltage slew.
[0] Undershoot interrupt.
5 INTELLIGENT ENERGY MANAGEMENT
Description
Description
Initial State
0
0
0
0
0
0
0
0
Initial State
0
0
0
0
0
0
0
0
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