Samsung S5PC110 Manual page 330

S5PC110_UM
3.7.3.9 Clock Source Control Registers (CLK_SRC_MASK1, Address = R/W, 0xE010_0284)
CLK_SRC_MASK1
Reserved
FIMC_LCLK_MASK
F1
F0
Reserved
Bit
[31:7] Reserved
[4] Mask output clock of MUXFIMC_LCLK
(0: disable, 1: enable)
[3] Should have same value as FIMC_LCLK_MASK
[2] Should have same value as FIMC_LCLK_MASK
[1:0] Reserved
Description
3 CLOCK CONTROLLER
Initial State
0x7FF_FFFF
1
1
1
0x3
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