Samsung S5PC110 Manual page 295

Risc microprocessor
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S5PC110_UM
2.2.60.17 External Interrupt Control Registers (EXT_INT_0_PEND, R/W, Address = 0xE020_0F40)
EXT_INT_0_PEND
Reserved
EXT_INT_0_PEND[7]
EXT_INT_0_PEND[6]
EXT_INT_0_PEND[5]
EXT_INT_0_PEND[4]
EXT_INT_0_PEND[3]
EXT_INT_0_PEND[2]
EXT_INT_0_PEND[1]
EXT_INT_0_PEND[0]
2.2.60.18 External Interrupt Control Registers (EXT_INT_1_PEND, R/W, Address = 0xE020_0F44)
EXT_INT_1_PEND
Reserved
EXT_INT_1_PEND[7]
EXT_INT_1_PEND[6]
EXT_INT_1_PEND[5]
EXT_INT_1_PEND[4]
EXT_INT_1_PEND[3]
EXT_INT_1_PEND[2]
EXT_INT_1_PEND[1]
EXT_INT_1_PEND[0]
Bit
[31:8]
Reserved
[7]
0 = Not occur
1 = Occur interrupt
[6]
0 = Not occur
1 = Occur interrupt
[5]
0 = Not occur
1 = Occur interrupt
[4]
0 = Not occur
1 = Occur interrupt
[3]
0 = Not occur
1 = Occur interrupt
[2]
0 = Not occur
1 = Occur interrupt
[1]
0 = Not occur
1 = Occur interrupt
[0]
0 = Not occur
1 = Occur interrupt
Bit
[31:8]
Reserved
[7]
0 = Not occur
1 = Occur interrupt
[6]
0 = Not occur
1 = Occur interrupt
[5]
0 = Not occur
1 = Occur interrupt
[4]
0 = Not occur
1 = Occur interrupt
[3]
0 = Not occur
1 = Occur interrupt
[2]
0 = Not occur
1 = Occur interrupt
[1]
0 = Not occur
1 = Occur interrupt
[0]
0 = Not occur
1 = Occur interrupt
2 GENERAL PURPOSE INPUT/ OUTPUT
Description
Description
Initial State
0
0
0
0
0
0
0
0
0
Initial State
0
0
0
0
0
0
0
0
0
2-260

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