S5PC110_UM
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VECTORED INTERRUPT CONTROLLER
1.1 OVERVIEW OF VECTORED INTERRUPT CONTROLLER
The interrupt controller in S5PC110 is composed of four Vectored Interrupt Controller (VIC), ARM PrimeCell
PL192 and four TrustZone Interrupt Controller (TZIC), SP890.
Three TZIC's and three VIC's are daisy-chained to support up to 93 interrupt sources. The TZIC provides a
software interface to the secure interrupt system in a TrustZone design. It provides secure control of the nFIQ
interrupt and masks the interrupt source(s) from the interrupt controller on the non-secure side of the system
(VIC). Use the latter to generate nIRQ signal.
To generate nFIQ from the non-secure interrupt sources, the TZIC0 takes the nNSFIQIN signal from the non-
secure interrupt controller.
1.1.1 KEY FEATURES OF VECTORED INTERRUPT CONTROLLER
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Supports 93 vectored IRQ interrupts
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Fixed hardware interrupts priority levels
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Programmable interrupt priority levels
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Supports Hardware interrupt priority level masking
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Programmable interrupt priority level masking
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Generates IRQ and FIQ
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Generates Software interrupt
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Test registers
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Raw interrupt status
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Interrupt request status
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Supports Privileged mode for restricted access
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1 VECTORED INTERRUPT CONTROLLER
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