Samsung S5PC110 Manual page 569

S5PC110_UM
CONCONTROL
drv_en
ctc_rtr_gap_en
aref_en
out_of
Reserved
Bit
[7] PHY Driving
0x0 = Disables
0x1 = Enables
During the high-Z state of the memory bidirectional pins, PHY
drives these pins with the zeros or pull down these pins for
preventing current leakage. Set PhyControl1.drv_type register
to select driving type.
[6] Read Cycle Gap for Two Different Chips
0x0 = Disables
0x1 = Enables
To prevent collision between reads from two different memory
devices, a one-cycle gap is required. Enable this register to
insert the gap automatically for continuous reads from two
different memory devices.
[5] Auto Refresh Counter
0x0 = Disables
0x1 = Enables
Enable this to decrease the auto refresh counter by 1 at the
rising edge of the mclk.
[4] Out of Order Scheduling
0x0 = Disables
0x1 = Enables
The embedded scheduler enables out-of order operation to
improve SDRAM utilization
[3:0] Should be zero
Description
1 DRAM CONTROLLER
Initial
R/W
State
R/W 0x0
R/W 0x1
R/W 0x0
R/W 0x1
0x0
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