S5PC110_UM
2.2 FUNCTIONAL DESCRIPTION
SROM Controller supports SROM interface for Bank0 to Bank5.
2.2.1 NWAIT PIN OPERATION
If the WAIT signal corresponding to each memory bank is enabled, the external nWAIT pin should prolong the
duration of nOE while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the
next clock after sampling nWAIT is high. The nWE signal has the same relation with nOE signal.
HCLK
ADDR
nGCS
nOE
nWAIT
DATA(R)
Tacs
Tcos
Figure 2-2
SROM Controller nWAIT Timing Diagram
tRC
Tacc=4
2 SROM CONTROLLER
Delayed
Sampling nWAIT
2-2