Samsung S5PC110 Manual page 585

S5PC110_UM
1.4.1.14 PHY Status Register (PhyStatus, Read Only, Address=0xF000_0040, 0xF140_0040)
PHYSTATUS0
Reserved [31:14]
ctrl_lock_value [13:4]
Reserved
ctrl_locked
ctrl_flock
ctrl_clock
Bit
Should be zero
Locked Delay
Locked delay line encoding value
ctrl_lock_value[9:2]: number of delay cells for coarse lock
ctrl_lock_value[1:0]: control value for fine lock
[3] Should be zero
[2] DLL Lock
0 = Unlocks DLL
1 = Locks DLL
[1] Fine Lock Information
It is indicated that DLL is locked with fine resolution, "phase
offset error" is less than 80ps.
[0] Coarse Lock Information
It is indicated that DLL changes step delays of the "delay line"
and "phase offset error" is less than 160ps.
Description
1 DRAM CONTROLLER
Initial
R/W
State
0x0
R 0x0
0x0
R 0x0
R 0xX
R 0xX
1-42