Onenand Interface; Overview Of Onenand Interface - Samsung S5PC110 Manual

S5PC110_UM

3.6 ONENAND INTERFACE

3.6.1 OVERVIEW OF ONENAND INTERFACE

The OneNAND interface is an AHB slave module that provides an interface for the AHB master to access
OneNAND devices on the internal AHB bus of OneNAND controller. For example,
1. The external AHB master can access OneNAND device through the AHB2AHB bridge and OneNAND
interface (Figure
3-2)
2. The internal AHB master can access the OneNAND deice through the OneNAND interface
Figure 3-9).
The OneNAND interface slave has few AHB transaction constraints. It supports HSIZE of HALFWORD and
WORD transactions on the AHB system bus. It also supports HBURST of SINGLE, INCR4, INCR8, and INCR16.
This interface outputs HRESP of ERROR at the first data phase of AHB transaction.
Both OneNAND and Flex-OneNAND flash memory devices are supported by OneNAND controller.
Both mux-type and demux-type OneNAND devices are supported by OneNAND controller. Use SFR to configure
the OneNAND device type.
Both asynchronous and synchronous read/ write operations are supported by OneNAND controller for OneNAND
flash memory devices. This mode of read/ write operations can be configured through the SFR. For more
information, refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register.
To connect OneNAND controller with eight OneNAND devices, eight chip enable (CE) signals are provided.
Asynchronous FIFOs are used for speed matching between OneNAND flash memory and AHB system bus. The
clock frequency relationship between OneNAND device and AHB system bus is fully asynchronous.
The OneNAND device supports only 16-bit data bus width. On the other hand, the OneNAND controller supports
32-bit AHB data bus width. While reading data from OneNAND device and writing that data to FIFO, the
OneNAND interface automatically resolves the data bus width mismatch. This interface also resolves the data bus
width mismatch while reading data from FIFO and writing that data to OneNAND device.
32-entry read prefetch FIFO supports read prefetching. This feature accelerates the sequential read performance
of OneNAND BootRAM and DataRAM areas. Use SFR to enable or disable this feature. For more information,
refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register.
To accelerate the write performance of the OneNAND DataRAM area, perform posted write. This feature is
implemented using the 32-entry posted write FIFOs.
Use SFR to configure the strobe signals' timing for asynchronous read/write operation. For more information, refer
to the OneNAND Interface Asynchronous Timing Control (ONENAND_IF_ASYNC_TIMING_CTRL) register.
Use SFR to configure the burst read write latency (BRWL) for the synchronous read/ write operation with 3, 4, 5,
6, and 7. For more information, refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register.
The OneNAND interface does NOT support the initial read write latency control through the RDY pin of the
OneNAND device.
The Burst Length (BL) also can be configured to 4-/ 8-/16-/ 32-/ 1024-burst and continuous burst through the SFR.
For more information, refer to the OneNAND Interface Control (ONENAND_IF_CTRL) register.
3 ONENAND CONTROLLER
(Figure 3-10 and
3-11