Samsung S5PC110 Manual page 663

S5PC110_UM
4.5.2.11 NFCON Status Register (NFSTAT, R/W, Address = 0xB0E0_0028)
NFSTAT
Flash_RnB_GRP
RnB_TransDetect
_GRP
Reserved
Flash_nCE[3:0]
(Read-only)
MLCEncodeDone
MLCDecodeDone
IllegalAccess
RnB_TransDetect
Flash_nCE[1]
(Read-only)
Flash_nCE[0]
(Read-only)
Reserved
Flash_RnB
(Read-only)
Bit
[31:28] The status of RnB[3:0] input pin.
0 = NAND Flash memory busy
1 = NAND Flash memory ready to operate
[27:24] When RnB[3:0] low to high transition occurs, this bit is set and an
interrupt is issued if RnB_TransDetect_GRP is enabled. To clear
this, write '1'.
0 = RnB transition is not detected
1 = RnB transition is detected
Transition configuration is set in RnB_TransMode(NFCONT[8]).
[23:12] Reserved
[11:8] The status of nCE[3:0] output pin.
[7] When 4-bit ECC encodng is finished, this bit is set and an
interrupt is issued if MLCEncodeDone is enabled. The
NFMLCECC0 and NFMLCECC1 have valid values. To clear this,
write '1'.
1 = 4-bit ECC encoding is completed
[6] When 4-bit ECC decoding is finished, this bit is set and an
interrupt is issued if MLCDecodeDone is enabled. The
NFMLCBITPT, NFMLCL0, and NFMLCEL1 have valid values. To
clear this, write '1'.
1 = 4-bit ECC decoding is completed
[5] Once Soft Lock or Lock-tight is enabled and any illegal access
(program, erase) to the memory takes place, then this bit is set.
0 = Illegal access is not detected
1 = Illegal access is detected
To clear this value, write 1 to this bit.
[4] When RnB[0] low to high transition occurs, this bit is set and an
interrupt is issued if RnB_TransDetect is enabled. To clear this,
write '1'.
0 = RnB transition is not detected
1 = RnB transition is detected
Transition configuration is set in RnB_TransMode(NFCONT[8]).
[3] The status of nCE[1] output pin
[2] The status of nCE[0] output pin
[1] Reserved
[0] The status of RnB[0] input pin.
0 = NAND Flash memory busy
1 = NAND Flash memory ready to operate
Description
4 NAND FLASH CONTROLLER
Initial State
0xF
0x800
0xF
0
0
0
0
1
1
0
1
4-22