True Ide Udma Mode Timing Diagram - Samsung S5PC110 Manual

S5PC110_UM

5.8 TRUE IDE UDMA MODE TIMING DIAGRAM

The Ultra-DMA (UDMA) is a fast DMA protocol which supports six timing modes (mode 0 ~ 5). Mode 5 is the
fastest; it operates at 100MHz. This ATAPI host controller supports upto mode 4. It operates at 66MHz. Both host
and device driver perform CRC check during UDMA burst transfer. At the end of the burst, the host sends its CRC
result to the device. If the CRC result does not match, the driver reports an error in the error register and asserts
the ATA_INTRQ signal.
The following figures (Figure
and device interface signals for UDMA data transfer.
The timing parameters involved is tACKENV, tRP, tSS, tDVS, and tDVH.
•
tACKENV indicates the setup and hold times of DMACK (Before assertion or negation) and envelope time
(From DMACKn to STOP and HDMARDYn).
•
tRP indicates Ready-to-pause time.
•
tSS indicates time from STROBE edge to negation of DMARQ or assertion of STOP.
•
tDVS is time for which data is valid until STROBE edge.
•
tDVH is time from STROBE edge until data is invalid.
DMARQ
DMACK
DIOW
DIOR
CS0,CS1,
DA[2:0]
IORDY
RD
DD[15:0 ] or
DD[7:0]
5-6, Figure 5-7 and Figure 5-8) defines the relationships between host
5-5, Figure
tACKENV tACKENV
Figure 5-5 UDMA- In Operation (Terminated by Device)
5 COMPACT FLASH CONTROLLER
tACKENV
tDVS tDVH
CRC
tACKENV
5-9