Samsung S5PC110 Manual page 846

S5PC110_UM
2.5.1.2 Multi-Master I
•
I2CSTAT0, R/W, Address = 0xE180_0004
•
I2CSTAT2, R/W, Address = 0xE1A0_0004
•
I2CSTAT_HDMI_DDC, R/W, Address = 0xFAB0_0004
•
I2CSTAT_HDMI_PHY, R/W, Address = 0xFA90_0004
I2CSTAT
Mode selection
Busy signal status /
START STOP condition
Serial output
Arbitration status flag
Address-as-slave status
flag
Address zero status flag
Last-received bit status
flag
2
C-Bus Control/Status Register
Bit
2
[7:6]
I C-bus master/ slave Tx/Rx mode select bits.
00 = Slave receive mode
01 = Slave transmit mode
10 = Master receive mode
11 = Master transmit mode
2
[5]
I C-Bus busy signal status bit.
0 = read) Not busy (If read)
write) STOP signal generation
1 = read) Busy (If read)
write) START signal generation.
The data in I2CDS is transferred
automatically just after the start signal.
[4] 2
I C-bus data output enable/ disable bit.
0 = Disables Rx/Tx,
1 = Enables Rx/Tx
2
[3]
I C-bus arbitration procedure status flag bit.
0 = Bus arbitration successful
1 = Bus arbitration failed during serial I/O
2
[2]
I C-bus address-as-slave status flag bit.
0 = Cleared when START/STOP condition was detected
1 = Received slave address matches the address
value in the I2CADD
2
[1]
I C-bus address zero status flag bit.
0 = Cleared if START/ STOP condition is detected
1 = Received slave address is 00000000b.
2
[0]
I C-bus last-received bit status flag bit.
0 = Last-received bit is 0 (ACK was received).
1 = Last-received bit is 1 (ACK was not received).
Description
2 IIC-BUS INTERFACE
Initial State
00
0
0
0
0
0
0
2-14