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S3C80A5B
Samsung S3C80A5B Manuals
Manuals and User Guides for Samsung S3C80A5B. We have
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Samsung S3C80A5B manual available for free PDF download: User Manual
Samsung S3C80A5B User Manual (250 pages)
8-bit CMOS
Brand:
Samsung
| Category:
Computer Hardware
| Size: 1.35 MB
Table of Contents
Important Notice
6
Table of Contents
8
Chapter 1 Product Overview
20
Overview
20
S3C80A5B Microcontroller
20
Features
21
Block Diagram
22
Pin Assignments
23
Pin Descriptions
24
Pin Circuits
25
Pin Circuit Type 2 (Port 1)
26
Pin Circuit Type 4 (P2.1)
27
Chapter 2 Address Spaces
28
Overview
28
Program Memory (ROM)
29
Register Architecture
30
Internal Register File Organization
31
Register Page Pointer (PP)
32
Register Set 1
33
Register Set 2
33
Prime Register Space
34
Working Registers
35
Using the Register Pointers
36
Non-Contiguous 16-Byte Working Register Block
37
Register Addressing
38
Register File Addressing
39
Common Working Register Area (C0H-CFH)
40
4-Bit Working Register Addressing
41
Bit Working Register Addressing
42
8-Bit Working Register Addressing
43
Bit Working Register Addressing Example
44
System and User Stacks
45
Standard Stack Operations Using PUSH and POP
46
Chapter 3 Addressing Modes
47
Overview
47
Register Addressing Mode (R)
48
Indirect Register Addressing Mode (IR)
49
Indirect Register Addressing to Program Memory
50
Indirect Working Register Addressing to Register File
51
Indirect Working Register Addressing to Program or Data Memory
52
Indexed Addressing Mode (X)
53
Indexed Addressing to Program or Data Memory with Short Offset
54
Indexed Addressing to Program or Data Memory
55
Direct Address Mode (DA)
56
Direct Addressing for Call and Jump Instructions
57
Indirect Address Mode (IA)
58
Relative Address Mode (RA)
59
Immediate Mode (IM)
60
Overview
61
Mapped Registers (Set 1)
62
Register Description Format
64
Basic Timer Control Register
65
Counter a Control Register
66
System Clock Control Register
67
External Memory Timing Register
68
System Flags Register
69
IMR Interrupt Mask Register
70
IPH Instruction Pointer (High Byte)
71
IPL Instruction Pointer (Low Byte)
71
IPR Interrupt Priority Register
72
IRQ Interrupt Request Register
73
Port 0 Control Register (High Byte)
74
Port 0 Control Register (Low Byte)
75
Port 0 Pull-Up Resistor Enable Register
78
Port 1 Control Register (High Byte)
79
Port 1 Control Register (Low Byte)
80
Port 2 Control Register
82
PP Register
83
RP0 Register Pointer 0
84
RP1 Register Pointer 1
84
SPL Stack Pointer (Low Byte)
85
SYM System Mode Register
86
Timer 0 Control Register
87
Chapter 11 Timer 1 Overflow Interrupt
88
Timer 1 Control Register (T1CON)
88
Chapter 12 Counter a
89
Overview
89
Chapter 4 Control Registers
90
Chapter 5 Interrupt Structure
90
Interrupt Types
90
S3C80A5B Interrupt Structure
91
S3C80A5B Interrupt Structure
92
Interrupt Vector Addresses
93
S3C80A5B Interrupt Vectors
94
Enable/Disable Interrupt Instructions (EI, DI)
95
Interrupt Processing Control Points
96
Peripheral Interrupt Control Registers
97
System Mode Register (SYM)
98
Interrupt Mask Register (IMR)
99
Interrupt Priority Register (IPR)
100
Interrupt Priority Register (IPR)
101
Interrupt Request Register (IRQ)
102
Interrupt Pending Function Types
103
Interrupt Source Polling Sequence
104
Generating Interrupt Vector Addresses
105
Chapter 13 Electrical Data
107
Overview
107
Instruction Group Summary
108
Flags Register (FLAGS)
112
Flag Descriptions
113
Instruction Set Notation
114
Instruction Notation Conventions
115
Opcode Quick Reference
116
Condition Codes
118
Instruction Descriptions
119
ADC Add with Carry
120
ADD Add
121
AND Logical and
122
BAND Bit and
123
BCP Bit Compare
124
BITC Bit Complement
125
BITR Bit Reset
126
BITS Bit Set
127
BOR Bit or
128
BTJRF Bit Test, Jump Relative on False
129
BTJRT Bit Test, Jump Relative on True
130
BXOR Bit XOR
131
CALL Call Procedure
132
CCF Complement Carry Flag
133
CLR Clear
134
COM Complement
135
CP Compare
136
CPIJE Compare, Increment, and Jump on Equal
137
CPIJNE Compare, Increment, and Jump on Non-Equal
138
DA Decimal Adjust
139
DEC Decrement
141
DECW Decrement Word
142
DI Disable Interrupts
143
DIV Divide (Unsigned)
144
DJNZ Decrement and Jump if Non-Zero
145
EI Enable Interrupts
146
ENTER Enter
147
EXIT Exit
148
IDLE Idle Operation
149
INC Increment
150
INCW Increment Word
151
IRET Interrupt Return
152
JP Jump
153
JR Jump Relative
154
LD Load
155
LDB Load Bit
157
LDC/LDE Load Memory
158
LDCD/LDED Load Memory and Decrement
160
LDCI/LDEI Load Memory and Increment
161
Load Memory with Pre-Decrement
162
Load Memory with Pre-Increment
163
LDW Load Word
164
MULT Multiply (Unsigned)
165
Next
166
NOP no Operation
167
OR Logical or
168
POP Pop from Stack
169
POPUD Pop User Stack (Decrementing)
170
POPUI Pop User Stack (Incrementing)
171
PUSH Push to Stack
172
PUSHUD Push User Stack (Decrementing)
173
PUSHUI Push User Stack (Incrementing)
174
RCF Reset Carry Flag
175
RET Return
176
RL Rotate Left
177
RLC Rotate Left through Carry
178
RR Rotate Right
179
RRC Rotate Right through Carry
180
SB0 Select Bank 0
181
SB1 Select Bank 1
182
SBC Subtract with Carry
183
SCF Set Carry Flag
184
SRA Shift Right Arithmetic
185
Srp/Srp0/Srp1
186
Set Register Pointer
186
STOP Stop Operation
187
SUB Subtract
188
SWAP Swap Nibbles
189
TCM Test Complement under Mask
190
TM Test under Mask
191
WFI Wait for Interrupt
192
XOR Logical Exclusive or
193
Overview
194
Clock Status During Power-Down Modes
195
System Clock Control Register (CLKCON)
196
Chapter 8 System Reset
197
Interrupt with Reset(INTR)
198
System Reset Operation
199
Hardware Reset Values
200
Power-Down Modes
202
To Divide STOP Mode Releasing and por
203
Idle Mode
205
Summary Table of Stop Mode, and Idle Mode
206
Overview
207
Chapter 9
208
Port Data Registers
208
Port
209
Port 0 Interrupt Enable Register (P0INT)
210
Port 0 External Interrupt Control Register (P0INT)
211
Port
212
Port 1 Low-Byte Control Register (P1CONL)
213
Port
214
Port 2 Data Register (P2)
215
Chapter 10 Basic Timer and Timer 0
216
Module Overview
216
Basic Timer Function Description
218
Timer 0 Function Description
220
Simplified Timer 0 Function Diagram: PWM Mode
221
Basic Timer and Timer 0 Block Diagram
222
Configuring the Basic Timer
223
Programming Timer 0
224
Overview
226
Timer 1 Block Diagram
228
Timer 1 Control Register (T1CON)
229
Timer 1 Registers
230
Chapter 7 Clock Circuit
231
Overview
231
Counter a Block Diagram
232
Counter a Control Register (CACON)
233
Counter a Output Flip-Flop Waveforms in Repeat Mode
235
To Generate 38 Khz, 1/3Duty Signal through P2.1
236
To Generate a One Pulse Signal through P2.1
237
Overview
238
Absolute Maximum Ratings
239
Characteristics of Low Voltage Detect Circuit
241
Input Timing for External Interrupts (Port 0)
242
Operating Voltage Range of S3C80A5B
243
Chapter 6 Instruction Set
244
Overview
244
Pin SDIP Package Mechanical Data
245
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