Samsung S5PC110 Manual page 341

S5PC110_UM
3.7.5.5 Clock Gating Control Register (CLK_GATE_IP3, R/W, Address = 0xE010_046C)
CLK_GATE_IP3
Reserved
CLK_PCM2
CLK_PCM1
CLK_PCM0
CLK_SYSCON
CLK_GPIO
Reserved
CLK_TSADC
CLK_PWM
CLK_WDT
CLK_KEYIF
CLK_UART3
CLK_UART2
CLK_UART1
CLK_UART0
CLK_SYSTIMER
CLK_RTC
Reserved
CLK_SPI1
Bit Description
[31] Reserved
[30] Gating all clocks for PCM2
(0: mask, 1: pass)
[29] Gating all clocks for PCM1
(0: mask, 1: pass)
(DO NOT mask when I2S1 or SPDIF
is used)
[28] Gating all clocks for PCM0
(0: mask, 1: pass)
(DO NOT mask when I2S0 or SPDIF
is used)
[27] Gating all clocks for SYSCON
(0: mask, 1: pass)
[26] Gating all clocks for GPIO
(0: mask, 1: pass)
[25] Reserved
[24] Gating all clocks for TSADC
(0: mask, 1: pass)
[23] Gating all clocks for PWM
(0: mask, 1: pass)
[22] Gating all clocks for WDT
(0: mask, 1: pass)
[21] Gating all clocks for KEYIF
(0: mask, 1: pass)
[20] Gating all clocks for UART3
(0: mask, 1: pass)
[19] Gating all clocks for UART2
(0: mask, 1: pass)
[18] Gating all clocks for UART1
(0: mask, 1: pass)
[17] Gating all clocks for UART0
(0: mask, 1: pass)
[16] Gating all clocks for System Timer
(0: mask, 1: pass)
[15] Gating all clocks for RTC
(0: mask, 1: pass)
[14] Reserved
[13] Gating all clocks for SPI1
(0: mask, 1: pass)
3 CLOCK CONTROLLER
Gated Clock Name
-
PCLK_PCM2
SCLK_AUDIO2
PCLK_PCM1
SCLK_AUDIO1
PCLK_PCM0
SCLK_AUDIO0
PCLK_SYSCON
PCLK_GPIO
PCLK_TSADC
PCLK_PWM
SCLK_PWM
PCLK_WDT
PCLK_KEYIF
PCLK_UART3
SCLK_UART3
PCLK_UART2
SCLK_UART2
PCLK_UART1
SCLK_UART1
PCLK_UART0
SCLK_UART0
PCLK_ST
PCLK_RTC
PCLK_SPI1
SCLK_SPI1
Initial State
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3-44