Samsung S5PC110 Manual page 353

S5PC110_UM
3.7.8.2 Clock MUX Status SFRs (CLK_MUX_STAT1, R, Address = 0xE010_1104)
CLK_MUX_STAT1
DMC0_SEL
G2D_SEL
Reserved
HPM_SEL
Reserved
MFC_SEL
G3D_SEL
Bit
[31:28] Selection signal status of MUXDMC0
(00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL,
011x:SCLKVPLL, 1xxx: On changing)
[27:24] Selection signal status of MUXG2D
(00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL,
011x:SCLKVPLL, 1xxx: On changing)
[23:19] Reserved
[18:16] Selection signal status of MUXHPM
(001: SCLKAPLL, 010: SCLKMPLL, 1xx: On changing)
[15:8] Reserved
[7:4] Selection signal status of MUXMFC
(00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL,
011x:SCLKVPLL, 1xxx: On changing)
[3:0] Selection signal status of MUXG3D
(00x0:SCLKA2M, 00x1:SCLKMPLL, 010x:SCLKEPLL,
011x:SCLKVPLL, 1xxx: On changing)
Description
3 CLOCK CONTROLLER
Initial State
0x0
0x0
0x0
0x1
0x0
0x0
0x0
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