Samsung S5PC110 Manual page 601

S5PC110_UM
2.4.1.2 SROM Bank Control Register (SROM_BC: XrCSn0 ~ XrCSn2)
•
SROM_BC0, R/W, Address = 0xE800_0004
•
SROM_BC1, R/W, Address = 0xE800_0008
•
SROM_BC2, R/W, Address = 0xE800_000C
•
SROM_BC3, R/W, Address = 0xE800_0010
•
SROM_BC4, R/W, Address = 0xE800_0014
•
SROM_BC5, R/W, Address = 0xE800_0018
SROM_BCn Bit
Tacs [31:28]
Tcos [27:24]
Reserved [23:21]
Tacc [20:16]
Adress set-up before nGCS
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks
0011 = 3 clocks
.............
1100 = 12 clocks 1101 = 13 clocks
1110 = 14 clocks 1111 = 15 clocks
Note: More 1~2 cycles according to bus i/f status
Chip selection set-up before nOE
0000 = 0 clock
0001 = 1 clocks
0010 = 2 clocks
0011 = 3 clocks
.............
1100 = 12 clocks 1101 = 13 clocks
1110 = 14 clocks 1111 = 15 clocks
Reserved
Access cycle
00000 = 1 clock
00001 = 2 clocks
00001 = 3 clocks 00010 = 4 clocks
.............
11100 = 29 clocks
11101 = 30 clocks
11110 = 31 clocks
11111 = 32 clocks
Description
2 SROM CONTROLLER
Initial State
0000
0000
000
01111
2-9