Samsung S5PC110 Manual page 34

Table
Number
Table 3-1 APLL PMS Value ............................................................................................................................... 3-5
Table 3-2 MPLL PMS Value............................................................................................................................... 3-6
Table 3-3 EPLL PMS Value ............................................................................................................................... 3-6
Table 3-4 VPLL PMS Value ............................................................................................................................... 3-7
Table 3-5 Maximum Operating Frequency for Each Sub-block ....................................................................... 3-10
Table 3-6 Special Clocks in S5PC110 ............................................................................................................. 3-12
Table 3-7 I/O Clocks in S5PC110 .................................................................................................................... 3-13
Table 4-1 Comparison of Power Saving Techniques......................................................................................... 4-2
Table 4-2 S5PC110 Power Domains of Internal Logic ...................................................................................... 4-3
Table 4-3 Power Mode Summary ...................................................................................................................... 4-5
Table 4-4 Power Saving Mode Entering/Exiting Condition .............................................................................. 4-19
Table 4-5 Cortex-A8 Power Control ................................................................................................................. 4-23
Table 4-6 Relationship Among Power Mode Wakeup Sources ....................................................................... 4-25
Table 4-7 S5PC110 External Power Control.................................................................................................... 4-26
Table 4-8 The Status of MPLL and SYSCLK After Wake-Up .......................................................................... 4-29
Table 4-9 S5PC110 Internal Memory Control .................................................................................................. 4-31
Table 4-10 Register Initialization Due to Various Resets................................................................................. 4-37
Table 5-1 Example Divider Values for 1600MHz PLL Output.......................................................................... 5-13
Table 5-2 Example Divider Values for 833MHz PLL Output............................................................................ 5-13
Table 6-1 Functions Needed for Various Reset Status...................................................................................... 6-3
Table 6-2 First Boot Loader's Clock Speed at 24 MHz External Crystal ........................................................... 6-6
Table 6-3 OM Pin Setting for Various Booting Option ....................................................................................... 6-7
List of Tables
Title Page
Number