Samsung S5PC110 Manual page 359

S5PC110_UM
3.7.10.12 IEM Control SFRs
•
CLKDIV_IEM_L8, R/W, 0xE010_3200
•
CLKDIV_IEM_L7, R/W, 0xE010_3204
•
CLKDIV_IEM_L6, R/W, 0xE010_3208
•
CLKDIV_IEM_L5, R/W, 0xE010_320C
•
CLKDIV_IEM_L4, R/W, 0xE010_3210
•
CLKDIV_IEM_L3, R/W, 0xE010_3214
•
CLKDIV_IEM_L2, R/W, 0xE010_3218
•
CLKDIV_IEM_L1, R/W, 0xE010_321C
CLKDIV_IEM_L1 ~ 8
Reserved
HPM_RATIO
Reserved
COPY_RATIO
Reserved
HCLK_MSYS_RATIO
Reserved
APLL_RATIO
Each register of CLKDIV_IEM_L1~8 configures clock divider values for ARM and HPM clocks at IEM performance
level-1 to 8.
Bit
[31:23] Reserved
[22:20] DIVIEM clock divider ratio,
DIVIEM = DIVCOPY / RATIO (RATIO = IEM_RATIO + 1)
[19] Reserved
[18:16] DIVCOPY clock divider ratio,
DIVCOPY = MUXIEM / RATIO (RATIO = COPY_RATIO + 1)
[15:11] Reserved
[10:8] DIVHCLKM clock divider ratio,
HCLK_MSYS = ARMCLK / RATIO (RATIO =
HCLK_MSYS_RATIO + 1)
[7:3] Reserved
[2:0] DIVAPLL clock divider ratio,
ARMCLK = MUX_MSYS / RATIO (RATIO = APLL_RATIO +
1)
Description
3 CLOCK CONTROLLER
Initial State
0x000
0x0
0
0x0
0x00
0x0
0x0
0x0
3-62