Clock Control; Initialization Protocol - Samsung S5PC110 Manual

S5PC110_UM

3.4.2 CLOCK CONTROL

The OneNAND controller has three clock source inputs, namely, HCLK, OA_CLK_OUT, and O_CLK_2X. Bus
system interface gets AHB bus clock, HCLK. On the other hand, OneNAND controller core gets one controller
clock input, O_CLK_2X. It generates OneNAND memory clock output, OA_CLK_OUT, which is supplied to
external OneNAND flash memory. The clock frequency of OA_CLK_OUT is half the clock frequency of
O_CLK_2X.
You can set the frequency ratio in special function register (SFR) of the system controller. For more information
about clock ratio setting, refer to Section 2.3, "Clock Controller".To change the clock frequency ratio, perform
these steps:
1. Check OneNAND Read Write Busy (ORWB) bit of OneNAND Interface Status (ONENAND_IF_STATUS)
register to ensure there are no memory transfers.
2. Switch the clock ratio in the SFR of system controller.
3. Write to the clock ratio register.
4. Start the memory accesses.

3.4.3 INITIALIZATION PROTOCOL

3.4.3.1 Power On
After power on, the S5PC110 and OneNAND controller are initialized. Thereafter, OneNAND controller will
automatically configure itself to work with the OneNAND flash memory devices. This automatic configuration can
be achieved using one of the following:
•
Mux-type OneNAND or Demux-type OneNAND
•
Asynchronous read and write mode
•
Read prefetch disabled
3.4.3.2 Boot Code
On initialization, the OneNAND flash device will automatically load boot data in boot buffer.
To access this code, one or more reads to the boot address can be issued. This operation will happen
asynchronously until both OneNAND devices and OneNAND controller are configured to run in synchronous
mode.
To configure both OneNAND devices and OneNAND controller, update the OneNAND Interface Control
(ONENAND_IF_CTRL) register.
3 ONENAND CONTROLLER
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