Figure 4-2 Internal Operation During Power Mode Transition - Samsung S5PC110 Manual

S5PC110_UM
D-IDLE &
LOGIC =RET
STOP_ A LLCLK0
Disable all clocks
except for EPLL
SLEEP
STOP &
LOGIC=ON
D-IDLE &
LOGIC= RET
SLEEP
PWR_OFF
Power OFF
SLEEP
NORMAL
Write SFR
PWR_MODE /
STANDBYWFI
Wait CLKST OPACK /
STANDBYWFI
DIS_ AR MC LK
Mask ARMCLK
STOP_ BU S
Disable BUS
operation
STOP_ DR AM
Request DRAM
power-down
STOP_ ALLCLK1
Disable all clocks
D-IDLE &
LOGIC=ON
SYSCLK
Change SYSCLK
PWD N _ SUB
Power down
sub -blocks
DIS_ AR MIO
Clamping Cortex-A8
PWD N _ SRA M
Disable SRAM
PWD N _ A RM
Power down
Cortex-A8
(D-IDLE|D-STOP)&
LOGIC=RET LOGIC=ON
EN _FF_ RET
Enable F F retention
D-IDLE &
STOP| D-STOP|SLEEP
LOGIC=ON
ALIVE_GPIO
Change GPIO
selection
EN _PA D_ R ET
Enable PAD ret ention
EN _PA D_ GATE
Enable PAD gating
(CPGI)
(D-)STOP &
EN _ISO_ EN LOGIC=ON
Disable isolation cells
(ISO _EN)
DIS_ SC
Disable footer cells
(SCPRE, SCALL)
D-IDLE/
D-STOP/STOP
Figure 4-2 Internal Operation During Power Mode Transition
EN_ AR MCLK
IDLE
TOP_IDLE
RU N _ B US
Operation
RU N _ D RAM
enable/disable
sequece
RU N _ A LLCLK
D-IDLE &
LOGIC=ON
PLLCLK
PWU P_SUB
EN_ AR MIO
Enable Cortex-A8 I/O
PMU_TOP_GAT E.v PWU P_SRA M
PWU P_A RM
Power up Cortex -A8
(D-IDLE|D-STOP)&
LOGIC=ON
DIS_ FF_RET
Disable F F ret ention
TOP_GATED
D-IDLE &
LOGIC=ON
NORMA L_GPIO
DIS_ PAD _RET
S/W
enable/disable
sequece
DIS_ PAD _GA TE
(D-)STOP) &
LOGIC=ON DIS_ ISO _EN
Enable isolation cells
EN_ SC PRE/A LL
Enable all footer cells
OSC_ STABLE
PWR _STA BLE
4 POWER MANAGEMENT
IDLE/STOP
Reset ARM
Unmask ARMCLK
Enable BUS
operation
Enable DRAM
Enable all clocks
Change PLL FOUT
Power up
sub-blocks
Enable SRAM
STOP&
LOGIC=RET
STOP&
LOGIC=ON
Change GPIO
selection
D-IDLE &
LOGIC=RET
Disable PAD
retention
Disable PAD gating
(CPGI)
(ISO_EN)
(SCPRE, SCALL)
OSC stable
Power stable
SLEEP
4-18