Samsung S5PC110 Manual page 538

1 DRAM Controller ........................................................................................1-1
1.1 Overview of DRAM Controller.................................................................................................................. 1-1
1.1.1 Introduction of DRAM Controller....................................................................................................... 1-1
1.1.2 Key Features of DRAM Controller .................................................................................................... 1-1
1.1.3 Supports Clock frequency up to 200MHz Block Diagram ................................................................ 1-2
1.2 Functional Description ............................................................................................................................. 1-3
1.2.1 Initialization ....................................................................................................................................... 1-3
1.2.2 Address Mapping.............................................................................................................................. 1-6
1.2.3 Low Power Operation ....................................................................................................................... 1-8
1.2.4 Precharge Policy............................................................................................................................... 1-9
1.2.5 Quality of Service............................................................................................................................ 1-11
1.2.6 Read Data Capture......................................................................................................................... 1-14
1.3 I/O Description ....................................................................................................................................... 1-19
1.3.1 PAD Mux for Address Configuration............................................................................................... 1-20
1.4 Register Description............................................................................................................................... 1-21
1.4.1 Register Map .................................................................................................................................. 1-21
2 SROM Controller ........................................................................................2-1
2.1 SROM Controller...................................................................................................................................... 2-1
2.1.1 Overview of SROM Controller .......................................................................................................... 2-1
2.1.2 Key Features of SROM Controller.................................................................................................... 2-1
2.1.3 Block Diagram of SROM Controller.................................................................................................. 2-1
2.2 Functional Description ............................................................................................................................. 2-2
2.2.1 nWAIT Pin Operation........................................................................................................................ 2-2
2.2.2 Programmable Access Cycle ........................................................................................................... 2-3
2.3 I/O Description ......................................................................................................................................... 2-4
2.4 Register Description................................................................................................................................. 2-5
2.4.1 Register Map .................................................................................................................................... 2-5
3 OneNAND Controller..................................................................................3-1
3.1 Overview of OneNAND Controller ........................................................................................................... 3-1
3.2 Key Features of OneNAND Controller ..................................................................................................... 3-1
3.3 Controller Usage Expectations ................................................................................................................ 3-2
3.4 Functional Description of OneNAND ....................................................................................................... 3-3
3.4.1 Block Diagram of OneENAND Controller ......................................................................................... 3-3
3.4.2 Clock control ..................................................................................................................................... 3-4
3.4.3 Initialization Protocol......................................................................................................................... 3-4
3.5 Memory Map ............................................................................................................................................ 3-5
3.6 OneNAND Interface ............................................................................................................................... 3-11
3.6.1 Overview of OneNAND Interface.................................................................................................... 3-11
3.6.2 OneNAND Interface Configuration ................................................................................................. 3-12
3.6.3 OneNAND Device Interrupt Handling ............................................................................................. 3-15
3.6.4 DMA Engine Overview ................................................................................................................... 3-18
3.6.5 DMA Operation ............................................................................................................................... 3-19
3.7 I/O Interface ........................................................................................................................................... 3-21
3.8 Register Description............................................................................................................................... 3-22
3.8.1 Register Map .................................................................................................................................. 3-22
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