Samsung S5PC110 Manual page 325

S5PC110_UM
3.7.3.4 Clock Source Control Registers (CLK_SRC3, R/W, Address = 0xE010_020C)
CLK_SRC3
Reserved
FIMC_LCLK_SEL
F1
F0
Reserved
Bit
[31:24] Reserved
[23:20] Control MUXFIMC_LCLK, which is the source clock of
FIMC2 local clock
(0000: XXTI, 0001: XUSBXTI, 0010: SCLK_HDMI27M,
0011: SCLK_USBPHY0, 0100: SCLK_USBPH1, 0101:
SCLK_HDMIPHY, 0110: SCLKMPLL, 0111: SCLKEPLL,
1000: SCLKVPLL, OTHERS: reserved)
[19:16] Should have same value as FIMC_LCLK_SEL
[15:12] Should have same value as FIMC_LCLK_SEL
[11:0] Reserved
Description
3 CLOCK CONTROLLER
Initial State
0x00
0x0
0x0
0x0
0x0
3-28