Samsung S5PC110 Manual page 570

S5PC110_UM
1.4.1.2 Memory Control Register (MemControl, R/W, Address = 0xF000_0004, 0xF140_0004)
MEMCONTROL
Reserved [31:23]
bl [22:20]
num_chip [19:16]
mem_width [15:12]
mem_type [11:8]
add_lat_pall
dsref_en
tp_en
Bit
Should be zero
Memory Burst Length
0x0 = Reserved
0x1 = 2
0x2 = 4
0x3 = 8
0x4 = 16
0x5 ~ 0x7 = Reserved
In case of DDR2/ LPDDR2, the controller only supports burst
length 4.
Number of Memory chips
0x0 = 1 chip
0x1 = 2 chips
0x2 ~ 0xf = Reserved
Width of Memory Data Bus
0x0 = Reserved
0x1 = 16-bit
0x2 = 32-bit
0x3 ~ 0xf = Reserved
Type of Memory
0x0 = Reserved
0x1 = LPDDR
0x2 = LPDDR2
0x3 = Reserved
0x4 = DDR2
0x5 ~ 0xf = Reserved
[7:6] Additional Latency for PALL
0x0 = 0 cycle
0x1 = 1 cycle
0x2 = 2 cycle
0x3 = 3 cycle
If all banks precharge command is issued, the latency of
precharging will be tRP + add_lat_pall
[5] Dynamic Self Refresh
0x0 = Disables
0x1 = Enables
Refer to
"1.2.3.3 . Dynamic Self Refresh"
[4] Timeout Precharge
0x0 = Disables
0x1 = Enables
If tp_en is enabled, it automatically precharges an open bank
after a specified amount of mclk cycles (if no access has been
made in between the cycles) in an open page policy.
If PrechConfig.tp_cnt bit-field is set, it specifies the amount of
Description
1 DRAM CONTROLLER
Initial
R/W
State
0x0
R/W 0x2
R/W 0x0
R/W 0x2
R/W 0x1
R/W 0x0
R/W 0x0
R/W 0x0
1-27