Operation Of Serial Peripheral Interface - Samsung S5PC110 Manual

S5PC110_UM 3 SERIAL PERIPHERAL INTERFACE

3.2.1 OPERATION OF SERIAL PERIPHERAL INTERFACE

The SPI transfers 1-bit serial data between S5PC110 and external device. The SPI in S5PC110 supports the CPU
or DMA to transmit or receive FIFOs separately and to transfer data in both directions simultaneously. SPI has two
channels, TX channel and RX channel. TX channel has the path from Tx FIFO to external device. RX channel has
the path from external device to RX FIFO.
CPU (or DMA) must write data on the register SPI_TX_DATA, to write data in FIFO. Data on the register are
automatically moved to Tx FIFOs. To read data from Rx FIFOs, CPU (or DMA) must access the register
SPI_RX_DATA and data are automatically sent to the SPI_RX_DATA register.
3.2.1.1 Operation Mode
SPI has two modes, namely, master and slave mode. In master mode, SPICLK is generated and transmitted to
external device. XspiCS#, which is the signal to select slave, indicates data valid when XspiCS# is low level.
XspiCS# must be set low before packets are transmitted or received.
3.2.1.2 FIFO Access
The SPI supports CPU access and DMA access to FIFOs. Data size of CPU access and DMA access to FIFOs
are selected either from 8-bit, 16-bit, or 32-bit data. If 8-bit data size is selected, valid bits are from 0 bit to 7 bit.
User can define the trigger threshold to raise interrupt to CPU. The trigger level of each FIFO in port 0 is set by 4
bytes step from 0 byte to 252 bytes, and that of each FIFO in port 1 is set by 1 byte step from 0 byte to 63 bytes.
TxDMAOn or RxDMAOn bit of SPI_MODE_CFG register must be set to use DMA access. DMA access supports
only single transfer and 4-burst transfer. In TX FIFO, DMA request signal is high until TX FIFO is full. In RX FIFO,
DMA request signal is high if FIFO is not empty.
3.2.1.3 Trailing Bytes in the Rx FIFO
If the number of samples in Rx FIFO is less than the threshold value in INT mode or DMA 4 burst mode and no
additional data is received, the remaining bytes are called trailing bytes. To remove these bytes in RX FIFO,
internal timer and interrupt signal are used. The value of internal timer is set up to 1024 clocks based on APB BUS
clock. When timer value is zero, interrupt signal occurs and CPU can remove trailing bytes in FIFO.
3.2.1.4 Packet Number Control
SPI controls the number of packets to be received in master mode. Set SFR (PACKET_CNT_REG) to receive any
number of packets. SPI stops generating SPICLK if the number of packets is the same as PACKET_CNT_REG. It
is mandatory to follow software or hardware reset before this function is reloaded. (Software reset can clear all
registers except special function registers, but hardware reset clears all registers.)
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